Vertical transistors are attracting substantial interest for utilization in highly integrated circuitry. Vertical transistors have source, drain and channel regions arranged along a vertical axis. Vertical transistors may thus have a relatively small footprint over an underlying semiconductor substrate as compared to conventional transistors having source, drain and channel regions arranged along a horizontal axis.
A continuing goal of integrated circuit fabrication is to increase the level of integration. Related goals are to decrease the size of individual circuit components, and to decrease the spacings between individual circuit components.
Vertical transistors often comprise source, drain and channel regions arranged in a vertically-projecting pillar of semiconductor material, and comprise a transistor gate along an outer surface of such pillar. The transistor gates of the vertical transistors are thus within spaces between semiconductor material pillars. In theory the pillars can be formed to be tightly packed while still enabling functional vertical transistors to be constructed. However, in practice it is found to be difficult to form the gates of vertical transistors within tight spaces between the transistors. Accordingly, the size of the spaces between the transistors can be dictated by limitations of a fabrication process, rather than by the performance characteristics of the transistor devices. It would be desirable to develop new methods for fabrication of vertical transistors which can enable gates of such transistors to be formed within tighter spaces between the semiconductor material pillars of the transistors.